The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost. Despite groundbreaking advances in materials and fabrication, scaling planar device such as the conventional MOSFET has proven challenging. To overcome these challenges, circuit designers are looking to novel structures to deliver improved performance. One avenue of inquiry is the development of three-dimensional designs, such as a fin-like field effect transistor (FinFET). A FinFET can be thought of as a typical planar device extruded out of a substrate and into the gate. A typical FinFET is fabricated with a thin “fin” (or fin structure) extending up from a substrate. The channel of the FET is formed in this vertical fin, and a gate is provided over (e.g., wrapping around) the channel region of the fin. Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from multiple sides. This can be leveraged in a number of way, and in some applications, FinFETs provide reduced short channel effects, reduced leakage, and higher current flow. In other words, they may be faster, smaller, and more efficient than planar devices.
Continued FinFET scaling also presents critical challenges. For example, as FinFETs are scaled down through various technology nodes, gate stacks using gate dielectric materials having a high dielectric constant (e.g., high-k dielectrics) have been implemented. In implementing high-k/metal gate stacks, it is important to properly scale an equivalent oxide thickness (EOT) of the gate structure to improve device performance. However, an interfacial layer may be required between the gate dielectric layer (e.g., HfO2) and the channel, which also contributes to the EOT of the gate structure. Furthermore, the interfacial layer may affect the flat band voltage and/or threshold voltage of FinFETs. Therefore, as the scale of FinFETs decreases, the thickness and/or uniformity of the interfacial layer become more and more critical.
Therefore, what is needed is an improved multi-gate structure and fabrication method.